Seminar Announcement
May 6, Friday, 15:00-16:00am, Room 南一楼三层东电信系会议室

Provably Good Interconnect Synthesis for Nanometer VLSI Design
Prof. Shiyan Hu
Department of Electrical and Computer Engineering
Michigan Technological University, USA

Abstract
As the VLSI technology enters the nanoscale regime, interconnect delay
becomes the bottleneck of circuit performance. Interconnect synthesis which
includes buffer insertion and layer assignment is indispensable in the
physical synthesis flow. In this talk, I will first introduce the classical
dynamic programming based buffer insertion and layer assignment techniques.
I will then highlight our recent work on developing a new provably good
algorithm for the timing driven minimum cost buffer insertion problem. This
NP-hard problem has been studied for over a decade but there is little
success in designing efficient approximations. Our algorithm is the first
fully polynomial time approximation scheme which can approximate the optimal
solution within a factor of 1+e running in O(m2n2b/e3+n3b2/e) time for any
0 will briefly describe our recently developed congestion-aware buffer
insertion technique.

Biography
Prof. Shiyan Hu received the Ph.D. degree in Computer Engineering from Texas
A&M University, TX, USA, in 2008. He is currently an Assistant Professor in
the Department of Electrical and Computer Engineering at Michigan
Technological University, MI, USA, where he is the director of Michigan Tech
VLSI CAD Research Lab. He has been with IBM Austin Research Lab as a
Visiting Professor during summer 2010. His research interests are primarily
on VLSI Physical Design and Optimization, including interconnect
optimizations and low power optimizations. He has published over 50
technical papers in refereed journals and conferences and he received the
Best Paper Award Nomination from 2009 IEEE/ACM International Conference on
Computer-Aided Design (ICCAD). He is currently an Associate Editor for
Journal of Circuits, Systems and Signal Processing (Springer) and
International Journal of Electronics and Communications (Elsevier), and a
Guest Editor for VLSI Design Journal. He has served as the Technical Program
Committee (TPC) members for various conferences including ICCAD, ISPD,
ISQED, SOCC, ICCD, ISVLSI, ISCAS, VLSI-SoC, MWSCAS, APCCAS and PATMOS. He
was the TPC track chairs for ICCAD in 2011, MWSCAS in 2008 and 2009, and
APCCAS in 2008. He is a senior member of the IEEE.